This relates generally to integrated circuits, and more particularly, to integrated circuits with memory circuitry.
Integrated circuits often contain memory elements such as random access memory (RAM) cells. Integrated circuits that include memory cells typically have thousands of data lines (DL). Hundreds of memory cells are attached to each data line. During typical read operations, each data line on an integrated circuit is precharged to a positive supply voltage. Because the length of each data line is long (e.g., hundreds of microns in length) and because each data line is connected to hundreds of memory cells, the capacitance of each data line is fairly large.
During typical precharge operations, large precharge transistors are used to precharge respective data lines across an entire integrated circuit. The large precharge transistors are used to precharge the data lines to a known positive supply voltage. Because the data line capacitances are large, precharging thousands of data lines simultaneously can result in a current surge (e.g., a surge on the order of 5 A in magnitude). The current surge can temporarily cause the internal power supply of the integrated circuit to sag to an undesirably low level. This raises a risk that the integrated circuit may fail to function properly.
Integrated circuits are also susceptible to process, voltage, and temperature (PVT) variations. It is difficult to accurately model these variations in simulation when designing conventional precharge circuitry. Conventional precharge transistors are therefore often over-designed (e.g., sized larger than necessary) to be able to function properly in worst case scenarios.
It would therefore be desirable to be able to provide improved precharge circuitry such as precharge circuitry that can minimize the current surge so that internal power supply voltages do not sag to low levels during precharge operations.